MegAmiga, the ultimate Amiga Extension board features all hardware your Amiga was waiting for decades ...
There are lots of people having an old Amiga lying around somewhere which is of no use at all any longer, because its floppy drive is already more or less dead and/or the floppy disks are unreadable, memory space is scarce and the OS is still on Kickstart 1.2.
On the other hand, there is a small community of Amiga enthusiasts still available. Prices for Amigas like the A1200/A3000/A4000 which can be used still today are as high as in the nineties. Amiga upgrades like memory extensions, turbo cards, network card or graphic controllers are sold at shockingly high rates on ebay.
Current electronic equipment is cheap an highly integrated. So why fiddle around with the SCSI hard drive controller from 1992 or find some old Kickstart images on ebay?
After a long fight with myself, whether it is still worth spending effort on my very first computer more than 30 years after its retirement, I decided to design the ultimate Amiga extension board covering all current interfaces on one single two layer PCB. In order to address the full remaining Amiga community it became an integrated 86 Pin Expansion port/Zorro-2/Zorro-3 card. Thus almost every Amiga is supported. Unfortunately my only two test candidates are an Amiga 500 and Amiga 2000 and therefore I focused my efforts on the 86 pin Expansion port and Zorro-2 development, as I don't have a chance to check the design on more recent Amiga models anyway. All Zorro-3 signals are routed to the CPLD. So feel free to develop your own Zorro-3 upgrade.
The board features:
- Three channel Hi-speed (480Mbit/s!) USB 2.0 on the go controller (NXP SAF1760/1761, like on E3B Deneb)
- 100base-T network adapter (Ax88796 based, like on the latest X-Surf 100 board)
- A1200/A4000 compliant IDE controller with compact flash socket and 44 pin IDE connector
- 4 MByte Flash memory to hold multiple Kickstart ROM images
- 16 MByte SDRAM (more memory is always useful)
- Push Button to emulate Amiga Action Replay functionality
- DIP Switches to turn features on or off
... so basically everything included to make your Amiga become again a more or less valuable member of your IT infrastructure.
And the best: The schematics, CPLD code and some application to get things up and running are available as open source.
The main component of the design is a Xilinx XC95XL288 CPLD in a 208 pin QFP package. As the Amiga runs with an IO voltage of 5V while all modern integrated circuits require 3.3V level shifting is required at all Amiga pins. As the CPLD is one of the last Xilinx devices having 5 Volt tolerant IO pins, it was chosen to handle the interface to the Amiga. Almost all relevant Zorro-2/3 and Amiga Extension Board pins (the latter is just a stripped down Zorro-2 slot) are directly connected to the CPLD ("southbound interface"). The Amiga is fine with the 3.3V output voltage of the CPLD as it uses mostly TTL logic.
The CPLD approach is highly flexible as every Amiga signal is available at the CPLD and we don't require additional level shifters or resistor arrays. The drawback of this approach is, that available logic resources are scarce (compared to an FPGA) and thus debugging becomes a nightmare as you can't place an internal logic analyzer inside the CPLD as you would do in an FPGA design.
The "northbound interface" comprises a parallel 3.3V address and data bus connecting the CPLD with the SDRAM, flash memory, Ethernet controller and USB controller. The control signals (CS, Read/Write, interrupt request) for each device are provided by the CPLD as well. The SDRAM control signals are provided by the CPLD separately. This allows us to run SDRAM activities like auto refreshes in the background without affecting IO operations on the internal address and data bus.
The Hard Disk Controller
Due to the limited pin count of the CPLD, the hard disk needed to be hooked up directly to the Amiga connector via a 16 bit bidirectional 3-state level shifter (74LVC16245). You can select the IO voltage on the IDE interface via resistors either to 3.3V or 5V. The control logic to handle the state of the level shifter as well as the control signals for the hard disc drive is implemented in the CPLD.
The SDRAM Controller
SDRAM works completely different to traditional "single access" DRAM, as you have to read/write a complete burst of data. However this doesn't really matter, as it is operated at a rate of 50 MHz, so you can easily perform a full read/write burst cycle within a standard Amiga IO access cycle. As the A500/A2000 address space is limited, only up to 8 MByte can be mapped to the address space at the same time. On a Zorro-3 implementation all 16 Mbyte could be made available at the same time.
The Flash Memory
The flash memory supports up to 4 Mbyte non volatile memory. It allows you to store a whole bunch of Kickstart images and would be also needed for an Amiga Action Replay implementation. As the addressable memory space is limited, only chunks of memory can be mapped at the same time.
The Ethernet Controller
An Ax88796 integrated 100 Base-T controller was implemented. The same device (but different package) is used on the latest X-Surf network adapters from IndividualComputers. So there is a chance, that a mostly X-surf compatible implementation can be done.
The USB Controller
The NXP SAF1760/1761 is one of the very few non PCI/PCIe USB host controllers available on the market. Unfortunately very hard to obtain (can be sourced from Aliexpress sometimes). Provides three high speed 480(!) Mbit/s USB interfaces. On the go functionality is available. However I don't have any idea, for what an OTG feature might be useful. So I implemented standard Type-A connectors to the board. While detailed technical documentation on the E3B Deneb USB controller is scarce, its feature set as well as the chip package one can assume that Deneb uses the same USB controller from NXP.
Getting everything down onto a two layer PCB turned out to be extremely challenging (but still possible).
The physical dimensions of Zorro-2 and Zorro-3 are identically (Zorro-3 uses some pins being unused on Zorro-2 or redefines some Zorro-2 signals). The 86pin Expansion port connector is almost identical to Zorro-2 but is lacking some pins. Thus you can turn a Zorro-2 card to an 86pin Expansion connector card. In order to fit the card into a standard A500 case, you need to cut off some of the excessive pins (i.e. pins 87 to 100). The location is marked on the PCB. I recommend cutting a groove into the PCB using a sharp knife or a Dremel tool and then breaking off the extra Zorro-2/3 pins. Take care you don't create any shorts on the cut PCB traces.
Although it might look tempting, be aware that you MUST NOT directly solder a 86pin connector (btw. also very hard to obtain) to the edge contacts of the MegAmiga board, as the top and bottom layers are swapped between the Zorror-2 and the Expansion board connector (to be more precise: The pins are equally enumerated, but A2000 provides the "female" slot connector on its PCB while the A500 provides the "male" part). As a result you will have to use the holes on the board to mount the appropriate Expansion board connector. Try to get some 90 degrees angled connectors somewhere (even harder to obtain), as otherwise the MegAmiga board will be perpendicular to the A500 PCB which pretty much sucks as it can easily lead to contact issues if you apply force to the PCB.
In order to keep costs down, the PCB is only as large as absolutely necessary. You might want to build some holder to keep the board in place in your Amiga. On an A2000/3000/4000 you might want to connect the USB connectors to some slot bracket as well. The design supports this by providing the standard 2x5pin USB pin headers found on any PC mainboard.
The CPLD design requires a significant amount of logic to be implemented into the CPLD
The Autoconfiguration Logic
The additional devices shall be mounted as different logical autoconfig cards:
- Ethernet Controller in IO space
- USB Controller in IO space
- Memory Extension (either flash memory or SDRAM) in RAM space
Each logical card has a base address register inside the CPLD which holds the desired starting address of the card in the Amigas memory space. This register is mapped to the Expansion Board space when the card is about to be configured by the operating system. This base address register is written by the operating system during bootup. After that the card maps itself to the assigned memory space.
The Hard Disk Controller
On the A1200/A4000 Gayle is used to generate the control signals for the IDE interface as well as the state of the level shifter. As Gayle is not available on Amiga without IDE controller the relevant IDE registers inside Gayle have to be implemented in the CPLD).
The SDRAM Controller
The SDRAM controller needs to initialize/configure the SDRAM at the beginning and afterwards needs to refresh the memory periodically in the background. This is done by a state machine inside the CPLD. Accesses to SDRAM need to be scheduled between these background activities.
Flash Memory as Kickstart Replacement
As the flash memory is not connected to the Kickstart socket, the chip select signal is not available to the MegAmiga and needs to be emulated by the CPLD as well. The CS signal is generated by Gary. Depending on the state of the OVL signal which is created by CIA1 (Odd CIA) the Kickstart memory is mapped to the end or at the beginning of the memory space. As the OVL signal is also not available to the board, we have to keep track the state of the responsible CIA register by monitoring accesses to the odd CIA and regenerate the OVL signal internally inside the CPLD.
USB and Ethernet
Accesses to the Amigas address space at the IO locations assigned during Autoconfiguration are routed to the internal address and data bus and the CS and R/W signals for the devices are generated accordingly.
Getting Things up and Running
The first PCBs for the A500 (86pin extension connector) and A2000 (Zorro-2) are available and initial tests were performed: The CPLD maps three autoconfig baords into the address space, the flash memory can be accessed, the Ethernet registers can be addressed, the Ethernet PHY is up and running.
It is highly recommended to build the board sequentially. At the time the Amiga was designed, wide parallel buses were the norm. A single unconnected or shorted signal may make the board respond to wrong addresses and/or may prevent the Amiga from booting. These issues are extremely hard to track down (trust me on that). By building the design sequentially and getting one feature up and running at a time, finding issues becomes much easier.
Call for Volunteers
Due to lack of spare time, MegAmiga development is stagnating. If you want to participate in the development of MegAmiga, seven gold plated bare MegAmiga PCBs are still available from the first batch, which I will provide at factory price (15 USD, including worldwide shipping and handling) to the first volunteers.
Be aware that you will need an Amiga (obviously), proficient fine pitch soldering skills, a Xilinx programming cable to get the CPLD code up and running and C/C++ software development skills as there are no device drivers yet. Additionally a logic analyzer would more than helpful to get things up and running. If you think you can handle this, feel free to contact me to speedup MegAmiga development.